One of the common elements required in electrical circuit devices is the simple pullup (or pulldown device) from an active device to one of the power supply buses. The pullup is simple if used to construct a circuit using discrete components in that all that is required is selecting a resistor of the desired resistance and tolerance, connecting it between an active device, such as an open collector transistor, and V.sub.cc and the transistor's output would be pulled up to V.sub.cc once the transistor is forward biased. With the advent of the integrated circuit (IC) however, fabricating a resistance onto a wafer substrate, such as silicon or gallium arsenide, takes special consideration particularly when resistivity and tolerances play an important part in circuit operation.
For example, as SRAMs have evolved from the small 4Kb memory arrays to more densely packed array sizes, tolerances of pullup resistances (or pullup loads) had to be tightly controlled. In order to minimize standby current many fabrication processes adopted using an active device as the pullup. In CMOS fabrication it is common to see a PMOS transistor acting an active load device, by providing a current path between a memory cell access transistor and the power supply bus. In this manner the PMOS transistor could be gated on only when the desired line was to be pulled to V.sub.cc and turned off otherwise, thereby virtually eliminating leakage current and minimizing standby current for the SR device as a whole. In still other CMOS circuits, the active PMOS device in combination with the active NMOS device creates the common CMOS inverter which is used throughout integrated circuit.
Conventional methods to fabricate an active pullup device, such as is the method of fabricating a PMOS active device by the use of selective epitaxially grown silicon (EPI), are expensive. As integrated circuits become more dense (i.e., as the SRAM generations continue to grow) cost becomes an even more critical factor that must be taken into account in order to produce competitively priced parts.
The present invention introduces a method to fabricate a self-aligning active PMOS device fabricated on top of an NMOS active device, thereby forming a CMOS inverter having a gate electrode being common to the two active devices. This fabrication technique provides for a less expensive method to form a CMOS inverter that may be used simply as an inverter or as a building block to construct an SRAM cell which results in reduced manufacturing cost compared to that of conventional CMOS fabrication processes.